Page buffer of non-volatile memory device and programming method of non-volatile memory device
US8189383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2011 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Feb 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.