Redundancy structures and methods in a programmable logic device
US8191025B1 · kind B1 · utility
3Cited by
29References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.