Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
US8191028B1 · kind B1 · utility
2Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Nov 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided to improve maximum operating frequency in an integrated circuit. Optimization may be performed during a route phase of a compilation process performed to generate a configuration of the integrated circuit. In some instances, useful clock skew is automatically determined and clock connectivity is rewired on a per-integrated circuit block (per-LAB) basis during the route phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.