Systems, methods, and computer products for compiler support for aggressive safe load speculation
US8191057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identifying both countable and non-countable loops, gathering a set of candidate loops for load speculation, and for each candidate loop in the set of candidate loops gathered for load speculation, computing an estimate of the iteration count, delay cycles, and code size, performing a profitability analysis and determining an unroll factor based on the delay cycles and the code size, transforming the loop by generating a prologue loop to achieve data alignment and an unrolled main loop with loop directives, indicating which loads can safely be executed speculatively and performing low-level instruction scheduling on the generated unrolled main loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.