MEMS process method for high aspect ratio structures
US8193005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3083
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.