Memory cells
US8193044B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Oct 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.