Methods of channel stress engineering and structures formed thereby

US8193049B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Oleg Golonzka · Beaverton, US
• Hemant Deshpande · Beaverton, US
• Ajay Sharma · Beaverton, US
• Cory E. Weber · Portland, US
• Ashutosh Ashutosh · Hillsboro, US

Key dates

• Filing date: Dec 17, 2008
• Grant date: Jun 5, 2012
• Expiry date: Dec 25, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/017

Abstract

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.