Inventor · Portland, OR, US

Cory E. Weber

48Patents
8h-index
71Co-inventors
78Inventor score

Filing activity: May 12, 1999 → Jan 10, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7226843B2 Indium-boron dual halo MOSFET Electricity 128 Expired
US7566605B2 Epitaxial silicon germanium for reduced contact resistance in field-effect transistors Electricity 13 Active
US6800887B1 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Electricity 12 Expired
US8193049B2 Methods of channel stress engineering and structures formed thereby Electricity 12 Active
US7226824B2 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Electricity 9 Expired
US10304946B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 9 Active
US7851291B2 Epitaxial silicon germanium for reduced contact resistance in field-effect transistors Electricity 8 Active
US9583487B2 Semiconductor device having metallic source and drain regions Electricity 8 Active
US7187057B2 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Electricity 7 Expired
US10411090B2 Hybrid trigate and nanowire CMOS device architecture Electricity 6 Active
US6410359B1 Reduced leakage trench isolation Electricity 6 Expired
US6215165A Reduced leakage trench isolation Electricity 5 Expired
US6838329B2 High concentration indium fluorine retrograde wells Electricity 4 Expired
US8779477B2 Enhanced dislocation stress transistor Electricity 4 Active
US7129533B2 High concentration indium fluorine retrograde wells Electricity 3 Expired
US10483385B2 Nanowire structures having wrap-around contacts Electricity 3 Active
US10600810B2 Backside fin recess control with multi-hsi option Electricity 2 Active
US11335789B2 Channel structures for thin-film transistors Electricity 1 Active
US11990476B2 Semiconductor nanowire device having (111)-plane channel sidewalls Electricity 0 Active
US11398478B2 Semiconductor nanowire device having (111)-plane channel sidewalls Electricity 0 Active
US12310044B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 0 Active
US10991696B2 Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing Electricity 0 Active
US12199098B2 Fin doping and integrated circuit structures resulting therefrom Electricity 0 Active
US9231076B2 Enhanced dislocation stress transistor Electricity 0 Active
US11342432B2 Gate-all-around integrated circuit structures having insulator fin on insulator substrate Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.