Asymmetric source and drain stressor regions
US8193065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2011 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | May 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.