Stacked-chip packaging structure and fabrication method thereof
US8193625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Mar 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.