Semiconductor package including multiple chips and separate groups of leads
US8193626B2 · kind B2 · utility
2Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Mar 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.