Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal
US8193828B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Jul 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/94094
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.