Integrated circuit of device for memory cell
US8194462B2 · kind B2 · utility
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15References
16Claims
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Key dates
| Filing date | Aug 12, 2011 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.