Nonvolatile semiconductor memory device
US8194467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.