Adaptive equalization methods and apparatus for programmable logic devices
US8194724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03783
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.