System and method to implement a matrix multiply unit of a broadband processor
US8195735B2 · kind B2 · utility
12Cited by
45References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Feb 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.