Bi-directional multi-drop bus memory system
US8195855B2 · kind B2 · utility
6Cited by
12References
22Claims
0Family size
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Key dates
| Filing date | Jun 3, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.