Processor power management and method
US8195887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Nov 2, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.