Silicon wafer for semiconductor and manufacturing method thereof

US8197594B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Katsuhiko Nakai · Yamaguchi, JP
• Wilfried von Ammon · Burghausen, DE
• Sei Fukushima · Yokohama, JP
• Herbert Schmidt · Friedberg, DE
• Martin Weber · Borgo San Lazzaro, DE

Key dates

• Filing date: Sep 19, 2007
• Grant date: Jun 12, 2012
• Expiry date: Mar 21, 2031

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T428/24992
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

Silicon wafers having a density of BMDs with sizes between 20 to 40 nm at positions ≧20 μm below the wafer surface in the range of 5×1011/cm3, and a density of BMDs with sizes of ≧300 nm≦1×107/cm3, exhibit reduced slip dislocation and warpage. The wafers are sliced from a crystal grown under specific conditions and then subjected to both low temperature heat-treatment and high temperature anneal.