Method for fabricating active device array substrate
US8198149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2012 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.