Annealing method for semiconductor device with silicon carbide substrate and semiconductor device
US8198182B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jan 19, 2011 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0291
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H2O to be not larger than 10−2 Pa, preferably not larger than 10−3 Pa, surface irregularity of the silicon carbide (SiC) substrate is controlled to be not greater than 2 nm, more preferably not greater than 1 nm in RMS value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.