Silicon-on-insulator structures for through via in silicon carriers
US8198734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Sep 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.