Techniques for sensing a semiconductor memory device
US8199595B2 · kind B2 · utility
7Cited by
184References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2010 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.