Integrating design for reliability technology into integrated circuits
US8201038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method executes computerized instructions within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics. The method performs an evaluation to determine whether the chip, component and sensor outputs are within predetermined limits, using the centralized programming interface; and reports occurrences of instances of the chip, component and sensor outputs being outside the predetermined limits, using the centralized programming interface, to an on-chip storage medium, external test equipment or computerized device outside of the packaged semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.