Method and apparatus for parallel ECC error location
US8201058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Apr 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1525
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.