Processor error checking for instruction data
US8201067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2008 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.