Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads
US8203860B2 · kind B2 · utility
1Cited by
2References
20Claims
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Key dates
| Filing date | Aug 3, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.