Patent · US Active

Architecture for efficient usage of IO

US8207754B2 · kind B2 · utility

4Cited by

11References

17Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Paras Garg · Noida, IN
Saiyid Mohammad Irshad Rizvi · New Delhi, IN

Key dates

Filing date	Feb 24, 2009
Grant date	Jun 26, 2012
Priority date	—
Expiry date	Feb 28, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/017509
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.