Patent · US Active

Digital phase lock loop

US8207770B1 · kind B1 · utility

7Cited by
6References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 23, 2010
Grant dateJun 26, 2012
Priority date—
Expiry dateDec 23, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L2207/50
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.