Operation method of memory device
US8208307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Dec 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.