Method and system to access memory
US8208315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2011 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Mar 21, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.