Semiconductor device, semiconductor package and memory repair method
US8208325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Sep 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.