Method and apparatus for memory test
US8208326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an integrated circuit that is configured for parallel memory testing. The integrated circuit includes a first memory block and a first scrambler coupled to the first memory block during a memory testing. The first memory block includes a first memory array, and a first envelope configured to translate a driving address of the first memory block into a corresponding physical address of the first memory array based on a first memory configuration for using the first memory array. The first scrambler is configured to provide a first plurality of driving addresses and associated first data to the first envelope based on the first memory configuration. The first plurality of driving addresses and the first data are used to test the first memory array according to a first test pattern. Further, the integrated circuit includes a second memory block and a second scrambler coupled to the second memory block during the memory testing. The second memory block includes a second memory array, and a second envelope configured to translate a driving address into a physical address of the second memory array based on a second memory configuration for using the sec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.