Live lock free priority scheme for memory transactions in transactional memory
US8209689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2007 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Apr 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.