3D chip-stack with fuse-type through silicon via
US8211756B2 · kind B2 · utility
15Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.