Method of fabricating integrated circuit with small pitch
US8211806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2007 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Jan 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.