Patent · US Active

Nanostructured memory device

US8212237B2 · kind B2 · utility

0Cited by
3References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 2, 2009
Grant dateJul 3, 2012
Priority date
Expiry dateJul 2, 2029

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S977/938
  • WIPO fieldMicro-structural and nano-technology
  • WIPO sectorChemistry

Abstract

The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.