Semiconductor device with improved insulating film and floating gate arrangement to decrease memory cell size without reduction of capacitance
US8212305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.