High-voltage transistor with improved high stride performance
US8212318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Feb 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.