Method for fabricating a backside through-wafer via in a processed wafer and related structure
US8212331B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2007 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a method for fabricating a backside through-wafer via in a processed wafer includes forming a through-wafer via opening through a substrate and extending the through-wafer via opening through at least one interlayer dielectric layer situated over the substrate. The method further includes forming a metal layer in the through-wafer via opening, where the metal layer forms an electrical connection to substrate. The metal layer is also in electrical contact with an interconnect metal segment situated above the at least one interlayer dielectric layer. The method further includes performing a thinning process to reduce the substrate to a target thickness before forming the through-wafer via opening. The method further includes forming an electrically conductive passivation layer on the metal layer and over a bottom surface of the substrate, where the electrically conductive passivation layer is in electrical contact with the metal layer and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.