Systems and methods for accelerating sub-pixel interpolation in video processing applications
US8212823B2 · kind B2 · utility
0Cited by
18References
18Claims
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Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Jun 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data path for a SIMD-based microprocessor is used to perform different simultaneous filter sub-operations in parallel data lanes of the SIMD-based microprocessor. Filter operations for sub-pixel interpolation are performed simultaneously on separate lanes of the SIMD processor's data path. Using a dedicated internal data path, precision higher than the native precision of the SIMD unit may be achieved. Through the data path according to this invention, a single instruction may be used to generate the value of two adjacent sub-pixels located diagonally with respect to integer pixel positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.