4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure
US8213227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Dec 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.