Methods of forming patterns in semiconductor devices
US8216944B2 · kind B2 · utility
1Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2010 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Jun 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.