Electrostatic discharge (ESD) protection device for use with multiple I/O standards
US8217457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2008 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Nov 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.