Non-volatile memory low voltage and high speed erasure method
US8218369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Jan 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.