Memory controller to utilize DRAM write buffers
US8219745B2 · kind B2 · utility
8Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Aug 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.