Multi-port high-level cache unit and a method for retrieving information from a multi-port high-level cache unit
US8219761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2005 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Jun 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.