Combined single error correction/device kill detection code
US8219880B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2011 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Sep 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.