Propagation delay time balancing in chained inverting devices

US8219950B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Jean-Luc Pelloie · Valbonne, FR
• Yves Thomas Laplanche · Valbonne, FR

Key dates

• Filing date: Mar 20, 2009
• Grant date: Jul 10, 2012
• Expiry date: Nov 9, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device.