Jean-Luc Pelloie
13Patents
4h-index
7Co-inventors
53Inventor score
Filing activity: Mar 17, 1992 → Dec 17, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8959472B1 | Considering compatibility of adjacent boundary regions for standard cells placement and routing | Physics | 21 | Active |
| US6787850B1 | Dynamic threshold voltage MOS transistor fitted with a current limiter | Emerging Cross-Sectional Technologies | 20 | Expired |
| US8134824B2 | Decoupling capacitors | Electricity | 9 | Active |
| US8381162B2 | Method of adapting a layout of a standard cell of an integrated circuit | Physics | 5 | Active |
| US10503859B2 | Integrated circuit design and/or fabrication | Electricity | 4 | Active |
| US6734483B2 | Process for fabricating a capacitor within an integrated circuit, and corresponding integrated circuit | Electricity | 3 | Expired |
| US9871039B2 | Resistance mitigation in physical design | Electricity | 3 | Active |
| US8924766B2 | Analysing timing paths for circuits formed of standard cells | Physics | 1 | Active |
| US8219950B2 | Propagation delay time balancing in chained inverting devices | Electricity | 1 | Active |
| US10452804B2 | Technique for distributing routing into superfluous metal section of an integrated circuit | Physics | 0 | Active |
| US5233307A | Process and apparatus for the qualification of a capacitive system | Physics | 0 | Expired |
| US12148697B2 | Devices and methods of local interconnect stitches and power grids | Electricity | 0 | Active |
| US9734269B2 | Liberty file generation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.